The present invention is directed to integrated circuits and more particularly, to reducing leakage current of an integrated circuit while the integrated circuit is performing tasks.
Integrated circuit (IC) power consumption includes dynamic power consumption by active modules of the IC and static power consumption by both the active and inactive modules of the IC. Dynamic power consumption can be reduced by techniques such as frequency and voltage scaling for the active modules and by gating (turning off) the clock signals for inactive modules. Although static power consumption can represent a significant proportion of the total power consumption of an IC, these techniques do not reduce static power consumption.
Most ICs these days include built-in methods for testing the cells and modules from which the IC is constructed. One well known method is known as “scan” or scan-set testing. In scan-set testing, flip-flops or latches of the IC are connected in one or more daisy chains. A test vector is then propagated from the first latch in the chain to the last latch in the chain and then to an output pad. Passing various test vectors through the scan chain allows much of the logic or circuitry of the IC to be tested. An example of scan chain technology is the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture, commonly known as Joint Test Action Group (JTAG). In a normal, functional mode of operation, the latches receive and store values depending on the applications being executed by the IC, while in scan mode, input and output latches of the cells are connected so that, at each clock cycle, the latches store the next functional data input or output of the cell so that during scan testing, the test vectors can be propagated through the scan chains, with the first and last latches of the chain connected to an externally accessible JTAG port. Test input data, known as a test vector, is then applied to the JTAG port and shifted through the chain of registers under the control of test clock signals. Once the test signals for each latch are correctly positioned in the scan chain, the circuit is placed in normal operating mode for a defined number of operating clock cycles. The circuit is then returned to test mode and the states of the output latches are shifted through the scan chain and recovered at the JTAG port as test results. Typically, the same clock gating logic that controls the functional clock signals is used to control the application of test scan clock signals during scan testing, controlled by the automatic test equipment (ATE).
The leakage currents of gates can vary considerably as a function of the values (‘0’ or ‘1’) of the voltage signals applied to the gates. For example, a gate that receives a value of ‘1’ may have greater leakage current than if the same gate was receiving a value of ‘0’. The leakage currents of cells of ICs vary considerably as a function of the voltages applied to the cell inputs. FIG. 1 illustrates a basic NAND gate 100 as an example of a conventional standard cell. The NAND gate 100 has two PMOS transistors 102 and 104 whose source-drain paths are connected in parallel between a positive supply rail VDD and an output node 106 and two NMOS transistors 108, 110 whose source-drain paths are connected in series between the output node 106 and ground. Input voltages A are applied to the gates of the transistors 102 and 110 and input voltages B are applied to the gates of the transistors 104 and 108. The assertion of both the input voltages A and B at positive values leads to the greatest leakage current in the NAND gate, since the NMOS transistors 108 and 110 are switched ON and the leakage current flows through the resistance of the two OFF PMOS transistors 102 and 104 in parallel. A smaller leakage current is obtained if one of the input voltages A and B is asserted and the other de-asserted, since one of the PMOS transistors 102 and 104 is ON and the leakage current corresponds to the resistance of the single one of the NMOS transistors 108 and 110, which is OFF. The smallest leakage current is obtained if both the input voltages A and B are de-asserted, since the leakage current corresponds to the resistances of both the OFF NMOS transistors 108 and 110 in series. Table 1 shows typical values obtained.
TABLE 1Leakage currentInputs(infinite load)% of smallestA = 0, B = 07.96 * 10−9A = 1, B = 04.58 * 10−8575%A = 0, B = 15.62 * 10−8706%A = 1, B = 11.88 * 10−72361%
Statistically the leakage current of the NAND gate 100 can be reduced, by a factor of up to 23 by applying voltages A=0, B=0 to the inputs of the NAND gate when it is not currently active, instead of leaving the inputs at the values (such as A=1, B=1) that they had after the last active state of the gate. Major reductions in leakage current can similarly be obtained for other types of cells such as NOR gates, XOR gates or multiplexers.
FIG. 2 illustrates a conventional electronic module 200 in an IC having individual data processing cells 202 and respective input and output latches 204. The latches 204 can also be connected in a test scan chain. In this example, each of the test scan chain elements includes a multiplexer 206 in addition to its latches 204. Each of the multiplexers 206 has an output connected to an input of the associated latch 204 and a first input connected to the output of the latch of the previous test scan chain element, except for the first and last test scan chain elements. The first input of the multiplexer of the first input test scan chain element receives a test data input signal TEST IN from the test access port. The output of the latch of the last test scan chain element provides a test data output signal TEST OUT to the test access port. The multiplexers receive from the test access port control signals TEST, comprising test mode and scan enable signals. Each of the input latches 204 has an output connected to a data input of the associated cell 202 and a second input of the associated multiplexer 206 connected to receive a functional data signal D. Each of the output latches 204 has its output connected to provide a data output signal D′, and a second input of the associated multiplexer 206 connected to a data output of the associated cell 202. The latches change state in response to the functional or test clock signals they receive, which also synchronize the operation of the associated cells 202.
In functional mode, the test enable signals set the multiplexers 206 to pass the data input and output signals D and D′ to and from the active latches 204 and data processing cells 202 without affecting the operation of the cells. The test mode signals set the clock gating logic to receive the functional clock signals. The operation of the active latches 204 and data processing cells 202 is synchronized by the functional system clock signals CLK. The functional clock signals for the inactive latches 204 and data processing cells 202 are gated, so that the latches, and the cells, do not change state, saving dynamic power consumption.
In test mode, the test mode signals set the clock gating logic to receive the test clock signals, which replace the functional clock signals CLK. The clock gating logic applies the test clock signals at the appropriate periods to the relevant latches which form the scan chain. The test enable signals set the multiplexers 206 to connect the scan chain elements in a scan chain, forming a shift register. Test data input signals TEST IN forming a test vector are then shifted through the shift register in synchronization with the test clock signals. Simultaneously, test data output signals TEST OUT are shifted through the shift register and can be recovered at the test access port. Once the test vector is correctly positioned in the scan chain, the scan chain is placed in normal operating mode for one (or more) cycles of the functional clock signals CLK. The circuit is then returned to test mode and the states of the output latches are shifted through the scan chain by the test clock signals and recovered at the test access port as test results.
The electronic module 200 may have a full boundary scan chain or the scan chain may cover only some of the inputs and outputs. Each scan chain element may connect with an individual cell or may connect with traces having more than one cell. The electronic module 200 also may include more than one scan chain and the scan chain or chains of more than one module may be connected in series to form a single scan chain. The test signals TEST and TEST IN may be provided by an ATE (not shown). The test signals may include test instruction codes to modify interconnections between scan chains.
It is possible to use the scan chain to introduce a low leakage vector (LLV) having the voltages for the inputs of the different cells of the circuit that place the cells in low leakage current configuration, as proposed by Abdollahi et al. in their paper “Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains”, Proceedings Fourth International Symposium on Quality Electronic Design, 2003; Page(s): 49-54. Abdollahi et al. propose scanning in the LLV while the IC is in a sleep or low power mode. While this is a good improvement in reducing static power consumption, it does not reduce static power consumption while the IC is in normal, functional mode.
It would be advantageous to reduce the leakage power of an IC even while the IC is performing tasks.